Stability analysis of a parallel packet switch with bufferless input demultiplexers

Abstract

A class of packet switching systems with inverse multiplexing of switched connections and/or flows (the SCIMUX architecture) has been previously proposed. Such systems open the possibility to use the readily available switch fabrics and port cards in order to build fully-functional packet switches, operating at rates much higher than those of their own components taken in isolation. While a comprehensive analytical study of such systems is in high demand, it remains a largely unexplored research area. We consider the parallel packet switch (PPS) architecture, which is a variation of the SCIMUX architecture with the switching core composed of multiple parallel independent switching planes, restricting our attention to the case with bufferless input demultiplexers. We formalize the notion of comparing degrees of congestion in the switches operating at the different port rates by introducing the concept of relative stability. We describe a family of traffic dispatch algorithms and prove that they are necessary and sufficient to guarantee relative stability of a switching plane in the PPS architecture. Finally, we obtain a tight lower bound on the number of required switching planes K, show that the equivalent core speedup bound is given by S/spl ges/K/[K/2], and prove that meeting these bounds is necessary and sufficient to achieve stability of the entire PPS core. Our results assume a work-conserving behavior of each switching plane without imposing any restrictions on the queuing structure and service discipline. They naturally generalize to the case of multiple traffic flows between the same pair of external ports and may be applied to QoS-aware switches. The described algorithms are fully distributed and do not require state information of any kind to be exchanged between the architecture components.