Analysis of On-Chip Asymmetric Coaxial Waveguide Structure for Chip Area Reduction

Abstract

Chip areas can be efficiently utilized when transmission lines designed for slow-wave propagation are used. Running two-dimensional simulations of a coplanar waveguide (CPW) and a simple floating-shield, slow-wave structure (S-CPW) demonstrate the limitations of the inductive and capacitive quality factors of transmission lines. This establishes a method of engineering the line inductance and capacitance to realize an asymmetric coaxial waveguide (ACW). The ACW is realized on-chip using ground metal placed around a center conductor. The ground metal include slotted top metal, which are normally used for pads, that caps the structure. Measurements show that the increased phase constant of the ACW, which determines the reduced physical length corresponding to the wavelength, is 3.3 times higher than that of the CPW and the microstrip line. Measurements are also shown for the slow-wave transmission line (SWTL) for comparison. All structures have been fabricated using a 90 nm complementary metal oxide semiconductor (CMOS) process for frequencies up to 110 GHz.