Analysis of Nanosheet Field Effect Transistor (NSFET) for device and circuit perspective

Abstract

This paper presents an analysis of Nanosheet Field Effect Transistor (NSFET) and Nanowire FET for device and circuit perspective with 7nm channel length. While simulating the above device TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is used as a dielectric. In this device sheet thickness is 5nm and sheet pitch is 10nm. TiN is used as a gate metal. These devices are termed as gate all around transistor. They have better control over short channel effect. High k material is used for reducing short channel effect by increasing gate control for channel length below 20 nm. But this also increases fringes capacitance due to which RC delay is increased. However, Nanosheet Field Effect Transistor (NSFET)have better RC delay and drive current. In these devices sheet width is variable and drive current increases with increase in sheet width. In this paper, 6T SRAM cell is explained. Static noise margin is found from the butterfly curve from which we realized that read noise margin of Nanowire is better than that of NSFET but write noise margin is better in NSFET. N curve is more appropriate for finding SRAM parameters because in this information about both voltage and current are available.