Analysis of multi-core cache coherence protocols from energy and performance perspective

Abstract

Multi-core processors are widely spread in today's computing environment. These processors provide high performance by executing programs independently on multiple cores. Multithreading helps programmer to execute tasks independently by utilizing underlying computing architecture appropriately. Multiple threads share common memory space. Shared memory architectures face the problem of cache coherence. Different techniques has been devised to keep caches coherent. These techniques have their own advantages and disadvantages. The prime aim of computer architects is to provide a much better computing environment along with high performance and less energy consumption. The processors required for smart phone devices have major concern with energy efficiency. Recent research shows that hybridization of cache coherence techniques is being carried out to achieve the goals like high performance, energy efficiency and scalability. This work gives a focus on analysis of existing cache coherence techniques independently. These techniques can be integrated together for hybridization of cache coherence techniques. In particular, the issues like performance analysis and energy consumption of snoopy and directory based cache coherence variants are addressed. Snoopy protocol performance gets affected due to on-chip traffic. It has been observed that MOESI CMP Token cache coherence protocol is energy and performance efficient than all other variants.