Abstract
Abstract. This article analyzes existing methods of verification of cache coherence protocols of scalable systems. Based on the research literature, the paper describes a method of formal parameterized verification of safety properties of cache coherence protocols. The paper proposes a design of a verification system for cache coherence protocols. The article analyzes the method in terms of development and examination of the corresponding Promela model of the German cache coherence protocol and discusses extension and automation of the method needed to adapt it to verification challenges of the Elbrus microprocessors. Keywords: formal verification; model checking; deductive verification; cache coherence protocol; Elbrus 1. Introduction Modern microprocessor systems are scalable – the number of cores per chip increases and chips are combined into clusters. Each processor of the system has access to the shared address space. However, memory is physically distributed among the processors in order to increase the bandwidth and reduce the latency to local memory. Thus, access to the local memory is faster than access to the remote memory. To decrease the memory bandwidth demands of a processor, processors are equipped with multilevel caches. Caching of shared data introduces the problem of cache coherence. To solve the problem, computer architects often use hardware mechanisms that implement cache coherence protocols. Concurrent work of many hardware devices (for example, cache and main memory controllers), which exchange information in accordance with a cache coherence protocol, results in a colossal size of the protocol’s state space. This, in turn, makes verification of cache coherence protocols an extremely hard task.
Highlights
Modern microprocessor systems are scalable – the number of cores per chip increases and chips are combined into clusters
According to the method of deductive verification, in order to prove Gp, it is necessary to develop an auxiliary assertion φ, which is an over-approximation of the state space, and show that φ implies p
In order to alleviate this problem, a tool may be developed, which would build an internal representation of the concrete Promela model, modify it according to the transformations, and produce the abstract model
Summary
Modern microprocessor systems are scalable – the number of cores per chip increases and chips are combined into clusters. Memory is physically distributed among the processors in order to increase the bandwidth and reduce the latency to local memory. Computer architects often use hardware mechanisms that implement cache coherence protocols. Concurrent work of many hardware devices (for example, cache and main memory controllers), which exchange information in accordance with a cache coherence protocol, results in a colossal size of the protocol’s state space. Scalability leads to the need for formal verification methods that are capable of adapting to it. As the size of systems increases, the fully automated method of model checking reaches its limits and can no longer be used due to the state space explosion problem. As a rule, existing formal approaches to verification are either inapplicable to industrial-strength microprocessor systems or require an enormous amount of manual work
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