Abstract
A critical issue in the design of high-speed ADCs relates to the errors that result from comparator metastability. Studied for flash architectures in the past, this phenomenon assumes new dimensions in pipelined converters, creating far more complex error mechanisms. This paper presents a comprehensive analysis of comparator metastability effects in pipelined ADCs and develops a method to predict the error behavior for a given input signal PDF Different error mechanisms are identified and formulated to obtain the probability of error versus the magnitude of error. An 8-bit 600 MS/s ADC fabricated in 65 nm CMOS technology has been used to assess the validity of the analytical results.
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