Analysis of Low Power and High Speed Phase Frequency Detectors for Phase Locked Loop Design

Abstract

Phase Locked Loop (PLL) usual replicated problems are different requirements like small acquisition time, maximum locking range and minimum phase error variance. To meet these requirements various phase frequency detector (PFD) designs are proposed. The major trend in wireless transceivers is towards single-chip CMOS integration. But the increase of MOS devices on a single chip will consume more power. The PFD designs are targeted for specific applications. Conventional, PFDNG, Dynamic, PtPFD are evaluated and a design MUX based PFD using TGCMOS is suggested. All these designs are simulated using HSPICE with 180 nm technology for 2.0 V. Results show that PFDNG has consumed less power 0.079mW because of less transistors but shows high propagation delay. TGCMOSPFD shows highest energy efficiency among all the designs.