Analysis of Linewidth Uniformity and Line Edge/Width Roughness in a 5 nm Logic SAQP Process

Abstract

As the semiconductor manufacturing design rules have been continually shrinking, the requirement in linewidth uniformity, linewidth roughness, line edge roughness, and overlay has been rising to stringent levels [1]. In a FinFET process, the fins are made with 193 nm immersion lithography together with the Self-Aligned Quadruple Patterning (SAQP) techniques. The linewidth uniformity, line edge roughness (LER) and linewidth roughness (LWR) are critical limiting factors in the process of SAQP as LER does not scale down with the dimensions of the devices. Three times the root mean square (3σ) is the most common LER characterization parameter. In this paper, we have conducted a SAQP process study on a typical film stack based on a 5 nm logic process flow. We will make the SAQP patterns with domestically made etching machine and Atomic Layer Deposition (ALD) tools and will characterize all etch steps within the mandrel 1 and spacer 1 of SAQP process in terms of variations. We will benchmark the measured data against required targets in linewidth uniformity and line edge/width roughness. Moreover, we will present and analyze the result of our study.