Abstract
The adoption of the digital/time converter (DTC) circuit in fractional-N phase-locked loops (PLLs) allows the realization of high-performance bang-bang digital PLLs suitable for wireless communications. In this paper, a general expression of the dynamic range required for the DTC is derived as a function of the order of the Delta-Sigma modulator driving the frequency-divider modulus. Based on this, it is shown how the combination of the DTC with the M-phase switching technique helps to relax the DTC dynamic range by a factor of M and reduce its nonlinearity. The effectiveness of the phase switching technique is demonstrated via behavioral-level simulation of a digital PLL in the case of first-, second-, and third-order Delta-Sigma modulator.
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