An Attachable Fractional Divider Transforming an Integer-N PLL Into a Fractional-N PLL with SSC Capability

Abstract

Phase locked loops (PLLs) are utilized in SoCs for automotive industry. In the industry, the system handles with satellite signals which are weak radio waves coming from space. Therefore, the output frequency of PLLs is carefully designed to avoid Electromagnetic Interference (EMI). Recently, Global Navigation Satellite System (GNSS) is becoming more common and available frequency bands for clocks are getting narrow (Fig. 1 (a)). That leads, in many products, replacement integer-N PLLs (Int-N PLLs) with fractional-N PLLs (Frac-N PLLs) is needed to obtain smaller output frequency steps than reference frequency. It is important to make Frac-N PLLs as soon as possible to meet a market opportunity. However, it takes long time to make them from scratch. One of answers would be Frac-N digital PLL whose most part is digital circuit which is quickly designed with RTL. However, most of them need time-to-digital converters (TDCs) to make phase quantization noise small [1], [2]. The TDC is a key analog block that requires long time to design and calibration which increases complexity. If we have a fractional divider (FDIV) to make a Frac-N PLL by just connecting to an Int-N PLL, it is useful. Some Frac-N PLLs [3], [4] have been published and they have FDIVs. In [3], extra coarse frequency control is needed to generate the frequency information, increasing complexity. In [4], two-step phase interpolation has been proposed to reduce $\Delta \sum$ quantization noise. However, one of phase interpolators (PIs) is put together with the phase detector. It is tough to apply this structure to ordinary PLLs.