Analysis of emitter efficiency enhancement induced by residual stress for in situ phosphorus-doped polysilicon emitter transistors

Abstract

This paper analyzes the enhancement of emitter efficiency in in situ phosphorus-doped polysilicon (IDP) emitter transistors, whose polysilicon emitter is crystallized from an in situ phosphorus-doped amorphous Si film. There are two factors that enhance the emitter efficiency of the IDP emitter. One is a potential barrier at the LDP/substrate interface produced by residual stress in the IDP layer. The other is a very thin oxide layer at the interface, which prevents epitaxial growth at the interface. We have distinguished between the emitter efficiency enhancement due to each of these two factors by analyzing the characteristics of three types of IDP emitter in which the residual stress and the thin oxide layer at the interface are controlled differently. We found that the potential barrier due to the residual stress increases the emitter efficiency from about two times to about eight times depending on the emitter size, and that the thin oxide layer at the interface increases the emitter efficiency by about three times.