Analysis of Digitally Controlled Delay Loop-Nand Gate For Glitch Free Design

Abstract

This paper presents a glitch free NAND based digitally controlled delay-lines for the avoidance of glitches. DCDL circuit uses control bits which can be generated using circuits called driving circuits. Different techniques of driving circuits are proposed to reduce the power consumption and the critical path delay. The proposed NAND based DCDLs have been designed in 90nm CMOS technology and it is adopted in the PLL application in order to reduce the power and delay time too. The analysis of present and proposed NAND based DCDL has been represented. Simulation result shows that the circuits designed with modified DCDL reduce both the power consumption and critical path delay.