Analysis of aligned polysilicon grain boundaries effects on the performance of large-grain polysilicon MOSFET

Abstract

Aligned polysilicon grain boundaries effects on the performance of the MOSFET fabricated on large-grain polysilicon-on-insulator (LPSOI) have been investigated. The LPSOI film of grain size ranging from 10 to 100 /spl mu/m is formed from amorphous silicon using MILC (metal induced lateral crystallization) and subsequent high temperature annealing. The grain boundaries (GBs) are found parallel to the crystallization direction and it is possible to align these GBs parallel (longitudinal) and perpendicular (latitudinal) to the direction of current flow in the channel region. The parallel GBs have shown minimum impedance to the conduction carriers, thus the parallel GB's devices are maintaining the high drive current, low threshold voltage, and steep subthreshold slope. However, it is the source of higher leakage current in the off-state, which causes an early device shortage especially in wide devices. On the other hand, perpendicular GBs in the channel region have shown high impedance to the conduction carriers that result in higher threshold voltage, lower current drive, and gentle subthreshold slope. A significant improvement in the device performance his been obtained with scaling. This analysis provides the guideline for the high performance LPSOI circuits for 3-D application.