Analysis of ALD Dielectric Leakage in Bulk GaN MOS Devices

Abstract

This study analyzes the ability of various processing techniques to reduce leakage current in vertical GaN MOS devices. Careful analysis is required to determine suitable gate materials in GaN MOSFETs since they are largely responsible for determination of threshold voltage, gate leakage reduction, and number of interface traps. SiO2, Al2O3, and HfO2 films were deposited by atomic layer deposition and subjected to treatments nominally identical to those seen in vertical GaN MOSFET fabrication. This work determines mechanisms for reducing gate leakage by reduction of surface contaminants and interface traps using pre-deposition cleans, elevated temperature depositions, and post-deposition anneals. Al2O3 is an ideal candidate for a MOSFET gate dielectric with a breakdown electric field near 802 MV/cm which is an improvement on other reported breakdown strengths for similar films. SiO2 films treated with an 850 C anneal for 30 minutes show significant reduction in leakage current densities while maintaining breakdown at 5.4 MV/cm. HfO2 films show higher sensitivity to high temperature annealing suggesting more research into surface cleans is necessary prior to incorporation into a vertical GaN MOSFET process.