Interface Trap Density Characterization of ALD Gate Dielectrics for GaN Power MOSFETs

Abstract

This study analyzes the changes in the density of interface traps (DIT) for various atomic layer deposition (ALD) gate dielectric films on gallium nitride (GaN) devices fabricated on bulk GaN substrates. Each film type has been chosen with an optimized insulator/semiconductor interface obtained through chemical cleans or post deposition annealing (PDA). Reduction in dielectric leakage and interface traps in MOSCAP devices may be used in order to understand how these mechanisms affect more complex devices such as vertical GAN MOSFETs. GaN MOSFET and MOSCAP devices are often investigated and implemented in power systems with applications ranging from electric vehicles (EVs) to smart power grids. The unique material properties of GaN such as wide bandgap, high breakdown voltage, and high electron mobility create unique advantages over traditional silicon FETs. Vertical GAN MOSFETs are better suited for higher voltage applications due to current flow and voltage drop perpendicular to the surface while also reducing required chip area for high operating voltages. Although there are many advantages of vertical GaN devices, such an architecture presents unique challenges that must be addressed before such devices may be implemented in high power applications, such as the requirement for a native substrate and the need to improve the gate dielectric interface. The interface between the gate dielectric and the semiconductor is crucial in order to reduce threshold voltage drift, leakage current, and the density charge traps. Previous work has shown the importance of DIT reduction with chemical cleans and PDAs. Accurate calculations of the density of interface traps (DIT) are vital to fully realize device operation and reliability. The choice between surface cleans and dielectric annealing as a leakage reduction technique is dependent on the material and available processing capabilities. While PDAs may reduce the dielectric breakdown strength, they have been found to reduce gate leakage current and improve device performance for most gate dielectrics. Several methods have been proposed for DIT characterization, including the voltage dependencies of low- and highfrequency capacitance (CV), conductance (GV), and surface potential (WY). DIT may be calculated from the surface potential of the dielectric using the quasi-static capacitance and the capacitance of the chosen gate dielectric. This work uses quasi-static CV and surface potential electrical characterization of GAN MOSCAPs to determine DIT of various gate dielectric materials treated with PDAs and chemical cleans. Optimization of such films on MOSCAPs will allow for implementation into vertical GAN MOSFET architectures. Interface trap density may be reduced by decreasing the capacitance associated with defects and surface contamination or by selection of a dielectric material with a lower dielectric constant. Fixed charges at the dielectric/semiconductor interface are manifested in hysteresis between forward and reverse voltage sweeps and may be the result of contamination prior to ALD or point defects in the material. Al,0. is an attractive gate dielectric material due to its dielectric constant, which may improve breakdown strength (Fig. 1), but it may suffer from higher memory charge between continuous bias sweeps. SiO, ALD films have lower breakdown and significantly lower leakage currents but show the lowest density of remaining fixed charges between sweeps, suggestive of the lowest DIT of the tested dielectrics (Fig. 2) with the addition of PDA. Results were verified by altering bias conditions during testing in order to accumulate and deplete interface charges. Minor plateaus in capacitance in forward bias indicate the presence of negative fixed interface charges. Additional characterization may be necessary to determine the optimal conditions for DIT reduction for HfO., films, including reduction in PDA temperatures in combination with improved substrate chemical cleans.