Analysis for Implementing Power-Efficient Convolutional Operators on FPGA Platforms

Abstract

Recently, research on FPGA-based accelerators for deep learning models has been actively conducted to overcome problems of GPUs such as power consumption, size, and price. FPGAs have the characteristic that hardware resource and power consumption vary depending on how the target logic is configured. This paper proposes a more power-efficient FPGA implementation method by analyzing the hardware resource and power consumption according to the implementation method and precision of the convolution operator, which is the core operation of CNN. As a result, proper utilization of DSP can increase the power efficiency of the convolution operator in FPGA design, and optimal CNN accelerator design is possible through a well-balanced implementation that considers the hardware resources required for the implementation of various operations other than the convolution operation (e.g., batch-normalization, activation function).