Analysis and verification of SoC design RTL parameters

Abstract

Nowadays multi-core SoCs or embedded SoCs have several hundred thousands of RTL design parameters distributed across different IP instances. Ideally, we need to verify each RTL design parameter in SoC verification. It is one of the most challenging tasks of SoC verification. In this paper, we are proposing a hybrid verification methodology for parameter verification to address this challenge. Here we extract all RTL design parameter of new SoC, working silicon SoCs and IP delivery database(s), and later we perform comparative analysis. We also perform this comparative analysis with SoC architecture parameter specification. And also we are proposing a framework for generating UVM(universal verification methodology) sequences for all parameters of relevant IPs. This methodology was applied in two of our SoC designs and we have found few architectural issues in the design. It improves the SoC verification quality and productivity significantly. This methodology has been proven useful and now it has become part of our SoC design methodology.