Analysis and synthesis techniques of router circuits

Abstract

Along with continuing advancement of network and chip technology, vast amount of new router designs will be designed and utilized in differentiated Internet-connected systems, on-chip interconnection in SoC, and evolving software-defined networks. In this research, from an analysis of current and future router designs, we observe that router designs share a common composition structure. We thus devised synthesis techniques based on the common composition structure. It allows designers specifying high-level and detailed router design decisions. Together with extensible parts of router designs organized in the common structure, it can produce desirable synthesizable Verilog router designs. We implemented the synthesis design that is based on a number of synthesis techniques and HDL configuration generation method. Experimental results show that our approach can effectively produce desirable synthesizable Verilog router designs.