Analysis and Simulation of Non-Blocking Multiple Input ATM Switches based on Input Queuing

Abstract

This paper studies the bursty traffic performance on non-blocking multiple input ATM switches. The interconnection network of the ATM switch is such that each input port maintains a separate queue of cells for each output port. A cell leaves its queue after receiving services of one time slot duration. When cells are served according to first-in-first-out (FIFO) strategy, then due to head-of-line (HOL) blocking the performance of the switch is degraded. In order to improve the performance of non-blocking ATM switches, we need to deal with the HOL blocking problem. It was shown by Karol et al through mathematical analysis and computer simulation that HOL blocking limits the throughput [5] of each input port to a maximum of 58.6% under uniform random traffic and much lower than that for bursty traffic. In this paper we have used the parallel iterative matching (PIM) technique to reduce the HOL blocking as described in [6]. In this work, link bandwidth is taken as 155.5 Mbps. So minimum delay suffered by a cell is 2.827 μs. Each input VBR source i, i=1, 2………N, is modelled by two state ON-OFF Interrupted Bernoulli Process (IBP). The switch throughput and mean cell delay are computed using simulation for different switch sizes. It has been observed by simulation that PIM technique increases throughput and reduces mean cell delay. These results are more suitable for providing better quality of service for real time bursty applications.