Analysis and optimization of the planar 6H-SiC ACCUFET

Abstract

This paper discusses the optimization of the planar 6H-SiC ACCUFET structure based upon analysis, simulations and experimental results. Two-dimensional numerical simulations demonstrate that the maximum electric field in the gate oxide can be kept below 3.5 MV cm −1 even at the maximum blocking voltage of 1500 V, by proper device design thereby eliminating the oxide rupture problem seen in SiC UMOSFETs. The trade-off between specific on-resistance and the maximum gate oxide electric field is obtained using simulations. The fabricated 6H-SiC unterminated devices had a blocking voltage of about 350 V with a specific on-resistance of 18 mΩ cm 2 at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 20% of the analytically calculated and simulated specific on-resistance for the same device. High temperature measurements show that the threshold voltage decreases with temperature and the accumulation channel mobility (∼125 cm 2 V −1 s −1) is almost independent of temperature. The specific on-resistance exhibited positive temperature coefficient, as opposed to the undesirable negative temperature coefficient observed on previously reported high voltage SiC MOSFETs.