Analysis and Design of Output-Capacitor-Free Low-Dropout Regulators With Low Quiescent Current and High Power Supply Rejection

Abstract

This paper summarizes and extends our discussions on the recently developed output-capacitor-free low-dropout regulators (LDRs) with low quiescent current and high power supply rejection (LQC-HPSR LDRs) for SoC power management applications. By modifying the biasing scheme in a cascoding-based high-PSR topology, quiescent current consumption is significantly reduced while high PSR over a wide frequency range is maintained. The operation principle of the LQC-HPSR LDRs is elaborated and comprehensive analysis of PSR at different frequency ranges is presented. Furthermore, a novel implementation with enhanced robustness is proposed to limit the internal voltage range and accelerate the start-up speed as well. Two 12 mA LQC-HPSR LDRs-the first has one and the second has two NMOS transistors cascoded to the core regulator-have been designed in a 0.35- μm CMOS process with active areas of 0.055 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.084 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. Experimental results showed that they had dropout voltages of 0.4 V and 0.6 V, and achieved PSRs better than -23.0 dB and -38.0 dB up to 50 MHz at full load while consuming quiescent currents of only 28.6 μA and 43.9 μA, respectively.