Analysis and Design of Millimeter-Wave Low-Power CMOS LNA With Transformer-Multicascode Topology

Han-Chih Yeh,Huei Wang,Ze-Yu Liao

doi:10.1109/tmtt.2011.2173350

Abstract

In this paper, the analysis and design of a CMOS multicascode configuration with a noise-reduction transformer topology are presented. Two low-power (LP), miniature, and wideband low-noise amplifiers (LNAs) were designed and fabricated for demonstration. One with a transformer triple-cascode configuration was designed at V -band, and the other with a transformer quadruple-cascode configuration was designed at Q -band. Both of the two LNAs were fabricated using 90-nm LP CMOS technology. To minimize the noise figure (NF) and maximize both the small-signal gain and 3-dB bandwidth, the noise-reduction transformers are designed and placed between transistors of the triple- and quadruple-cascode devices. Based on this approach, the Q -band LNA has a gain of 20.3 dB and an NF of 4.6 dB at 40 GHz, with a power consumption of 15 mW. Both of the LNA utilize a 3-V supply voltage, but the drain source voltage of each device in the multicascode configuration is below 1 V. The V -band LNA presents a gain of 12.7 dB from 43 to 58 GHz and a minimum NF of 4.7 dB at 62.5 GHz with a power consumption of 18 mW. The chip size of the V - and Q -band LNAs are 0.42×0.45 mm 2 and 0.45×0.48 mm 2 , including all the testing pads. Compared with the conventional cascode LNAs, the proposed transformer triple-cascode LNA has a better NF, wider 3-dB bandwidth, and lower power consumption, whereas the transformer quadruple-cascode LNA features even higher gain performance.

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