Abstract
This brief presents an all-digital first-order 1-bit $\Delta \Sigma $ time-to-digital converter (TDC) using a time-mode signal processing approach. Time integration is performed using a bi-directional gated delay line. The nonlinearity and timing errors of the time integrator are analyzed. The impact of feedback time on the performance of the TDC is analyzed. A design methodology effective in minimizing the impact of process uncertainty is developed. The TDC is designed in a TSMC 130-nm 1.2-V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show the TDC offers SNDR of 50.0 dB and ENOB of 8.0 over 731-kHz bandwidth at 33-MHz sampling frequency while consuming 175 $\mu \text{W}$ . The FOM of the TDC is 0.47 pJ/conv.
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