Abstract
This paper presents an all-digital 1-1 MASH $$\Delta \Sigma$$ time-to-digital converter (TDC) using time-mode signal processing. A cascode time adder with a raised inverter threshold voltage is proposed to minimize the deterministic timing error caused by the current mismatch of the discharge paths of the time adder. A differential time integrator consisting of a pair of identical single-ended time integrators is proposed to minimize the effect of the nonlinearities of the single-ended time integrator. The random and deterministic timing errors of the TDC are analyzed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the TDC exhibits 40 dB per decade noise-shaping at high frequencies. The cascode-configured discharge paths and raised threshold voltage of the load inverter improve the linearity of the TDC. The TDC achieves 1.9 ps time resolution over 48–415 kHz signal band while consuming 502 μW.
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