Analysis and design guidelines for customized logic families in CMOS

Abstract

The power, speed, area and energy constraints are the major user concerns, when it comes to choosing the appropriate logic family for new applications. This paper introduces customizable logic families and presents a comparative analysis of such logic families, to enable the user to make a robust choice. Energy efficiency has been identified as one of the most required features for modern electronic systems designed for achieving high performance and portability. The existing logic families are modified to improve the performance, speed, area and energy efficiency. The use of Domino logic introduces many design risks because of its sensitivity to noise, circuit and layout topologies. Some possible solutions to alleviate these problems (precharge, charge leakage etc.) have been discussed. This paper introduces reduced swing logic style called dynamic current mode logic (DyCML) that reduces both gate and interconnect power dissipation. Unlike current mode logic circuits, DyCML gates do not have a static current source, which makes DyCML a good candidate for portable devices and battery powered systems. The design and optimization of the circuits namely domino logic, current mode logic (CML) and differential static CMOS logic or differential cascode voltage swing logic (DCVSL) has been proposed on basic 180nm technology. It could be worked on for better results in terms of power dissipation, delay and area for 65nm, 45nm, 35nm and other technologies in future. The paper focuses on the analysis of the customizable logic family design based on the user requirement.