Analogously tunable delay line for on-chip measurements with sub-picosecond resolution in 90 nm CMOS

Abstract

An analogously fine-tunable delay line in a standard 90 nm CMOS technology is proposed for use in on-chip measurements of asynchronous digital circuit elements. The implemented delay line achieves a maximum delay of 155 ps together with the possibility to fine and coarse tune the delay. Owing to its truly analogue tuning it can overcome the limitation of the minimum step sizes found in digital controllable delay lines. Performance verification of a produced test chip showed that a timing resolution of sub-picosecond is attained. Therefore the timing resolution of the proposed delay line exceeds that of common digital delay lines.