Analog Domain Carrier Phase Synchronization in Coherent Homodyne Data Center Interconnects

Abstract

Analog domain signal processing is an attractive approach for the reduction of power consumption in high capacity short reach coherent links. An analog domain equalizer for coherent links, as part of an all-analog solution, was first proposed and demonstrated by our group earlier. In the present work, we focus on the proof-of-the-concept demonstration of a carrier phase synchronization chip designed in a 130 nm SiGe BiCMOS technology. The chip, along with other loop components, is able to compensate for the time varying phase offsets between the modulated signal and the local oscillator (LO) in coherent homodyne links. The chip's functionality has been validated experimentally for operation at 40 Gbps, i.e., for QPSK modulation at 20 Gbaud and 16-QAM modulation at 10 Gbaud, in polarization multiplexed-carrier based self-homodyne (PMC-SH) links. Integrating such circuits in advanced technology nodes, such as the 7 nm FinFET process, can lead to low-power, low-cost, and high capacity DCI solutions for short reach applications. Additionally, the analog signal processing (ASP) based approach can reduce the latency added by the DSP based solutions. This reduction can be significant in intra-rack ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$&lt; $</tex-math></inline-formula> 100 m), high SNR links, wherein the propagation delay and the latency added by the FEC engine are not too high.