Analog design criteria for high-granularity detector readout in the 65 nm CMOS technology

Abstract

This work is concerned with the study of the analog properties, in particular in terms of gain and noise performance, of MOSFET devices belonging to a 65 nm CMOS technology. Silicon vertex detectors at the next generation colliders will be read out by means of front-end electronics based on fabrication processes with minimum feature size in the 100 nm range. Among the more scaled CMOS technologies, the 65 nm node is starting to be considered by integrated circuit designers for the development of Application Specific Integrated Circuits in detector applications. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. Data obtained from the measurements of devices provide a powerful tool to establish design criteria in this nanoscale CMOS process for detector front-ends. A comparison with data coming from less scaled technologies, such as 90 and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.