An ultra-low power and offset-insensitive CMOS subthreshold voltage reference

Abstract

An ultra-low power and offset-insensitive CMOS voltage reference circuit is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed circuit can suppress the DC offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions, and improving the power supply ripple rejection (PSRR) are presented. The voltage reference is implemented in a 0.18μm CMOS process. Simulation results show that the reference can run with 0.8 V supply voltage, while the power consumption is only 62nW, and the PSRR of better than −43 dB over the full frequency range is achieved.