Abstract
The execution of two-dimensional (2D) layered material in the source-region of a silicon-based tunnel field-effect transistors (TFETs) is proposed for ultra-low-power (ULP) applications. In the present simulation-based study, the layered black phosphorus (B-Ph) with moderate value of bandgap and low effective mass is used in the source-region of the SOI (silicon-on-insulator) heterojunction dopingless TFET (HD-TFET). The investigations of device characteristics are done against the channel lengths ranging from 45 nm to 14 nm. The device offers promising subthreshold characteristics for ULP applications with extremely low subthreshold swing of 1.77 mV/Decade, and IonIoff ratio of ≈109. The analog and radio-frequency (RF) performances of the B-Ph/Si HD-TFET are observed promising for the possible implementation at circuit level. Moreover, the proposed device offers a high degree of linearity with the maximum compression point of −20dB. The numerical simulation of the proposed device is performed on ATLAS™, a two-dimensional (2D) device simulator from Silvaco.
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