An S–K Band 6-Bit Digital Step Attenuator with Ultra Low Insertion Loss and RMS Amplitude Error in 0.25 μm GaAs p-HEMT Technology

Abstract

This paper presents an ultra-wideband, low insertion loss, and high accuracy 6-bit digital step attenuator (DSA). To improve the accuracy of amplitude and phase shift of the attenuator, two innovative compensation structures are proposed in this paper: a series inductive compensation structure (SICS) designed to compensate for high frequency attenuation values and a small bit compensation structure (SBCS) intended for large attenuation bits. Additionally, we propose insertion loss reduction techniques (ILRTs) to reduce insertion loss. The fabricated 6-bit DSA core area is only 0.51 mm2, and it exhibits an attenuation range of 31.5 dB in 0.5 dB steps. Measurements reveal that the root-mean-square (RMS) attenuation and phase errors for the 64 attenuation states are within 0.18 dB and 7°, respectively. The insertion loss is better than 2.54 dB; the return loss is better than −17 dB; and the input 1 dB compression point (IP1 dB) is 29 dBm at IF 12 GHz. To the best of our knowledge, this chip presents the highest attenuation accuracy, the lowest insertion loss, the best IP1dB, and a good matching performance in the range of 2–22 GHz using the 0.25 μm GaAs p-HEMT process.