Abstract
This article presents a switched-capacitor (SC)-parallel-inductor buck (CPL-Buck) converter with reduced inductor voltage and current. The proposed CPL-Buck converter reduces the voltage stress on the power inductor with a series-connected flying capacitor in one phase, alleviating the current stress with a parallel-connected SC path in both phases. Therefore, it effectively lowers the average inductor current as well as its ripple, allowing the utilization of a small-volume inductor to deliver a large output current. In addition, to cover a wide voltage conversion ratio (VCR) range, the proposed CPL-Buck is able to operate in either a sub-1/3X mode or a sub-1/2X mode. This work, fabricated in 65-nm CMOS, occupies an area of 2.72 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . Measurement results show that the proposed CPL-Buck obtains a peak efficiency of 92.9% and a peak current density of 0.3 A/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> with a power inductor as small as 1.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.8 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{3}$</tex-math> </inline-formula> , with an input range of 3–4.2 V, an output range of 0.6–1 V, and 1.2-A maximum output current.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call