An output-capacitor-less flipped voltage follower based low dropout regulator with improved buffer impedance attenuation in 45 nm CMOS technology

Abstract

A flipped voltage follower (FVF) based low drop out (LDO) with fast transient response is presented here. A simple fast FVF stage is associated with an output impedance enhanced source follower driving gate of pass element for faster recovery during load transients. The proposed LDO is capable of driving 10’s of pF to 1nF capacitive loads while maintaining enough phase margin for stability. This LDO offers stable regulation upto 30 mA producing a regulated voltage of 1.10V with 1.2V dc supply. The LDO is implemented in 45 nm CMOS technology which consumes 72μA of quiescent current under full load of 30 mA. LDO achieves -18-22 dB of PSRR over the band of 1-1MHz, over entire range load current drive of 200A-30 mA. 1% settling time of 32.4 ns is achieved with 1nF capacitive for rising load transition of 30mA-200uA and 47.52 ns settling time for falling load transition of 200μA-30 mA. DC line and load regulations for a typical 100pF load are respectively around 0.018V/V and 1.8mV/30 mA. The regulated voltage of 1.1V is maintained during process corners and wide temperature ranges (-60 °C to 60 °C) for 1.2V supply.