A multi-loop low-dropout FVF voltage regulator with enhanced load regulation

Abstract

This paper introduces a multi-loop fast transient response flipped voltage follower (FVF) low-dropout (LDO) voltage regulator suitable for system-on-chip (SOC) applications. While typical FVF-based LDOs exhibit fast transient response, which is critical for SOC applications, their output DC accuracy is limited due to low loop gain of the FVF. In this work, we introduce a multi-loop design aimed at improving the DC accuracy while preserving the transient performance. The LDO is implemented in a 180-nm CMOS process to provide an output voltage of 1.5V at a maximum load current of 10mA from an input line voltage of 1.8V. The designed LDO's quiescent current is 53μA at minimum load. Simulation results showcase the advantages of the multi-loop design with a transient response time of 0.73ns and a figure of merit (FOM) of 3.9ps.