An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUs

Vijayalakshmi Saravanan,Isaac Woungang,Dwarkadas Pralhaddas Kothari,Kothari Dwarkadas Pralhaddas

doi:10.1186/s13673-014-0016-8

Vijayalakshmi Saravanan, Isaac Woungang + Show 2 more

Open Access

https://doi.org/10.1186/s13673-014-0016-8

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Abstract

AbstractThe power-performance trade-off is one of the major considerations in micro-architecture design. Pipelined architecture has brought a radical change in the design to capitalize on the parallel operation of various functional blocks involved in the instruction execution process, which is widely used in all modern processors. Pipeline introduces the instruction level parallelism (ILP) because of the potential overlap of instructions, and it does have drawbacks in the form of hazards, which is a result of data dependencies and resource conflicts. To overcome these hazards, stalls were introduced, which are basically delayed execution of instructions to diffuse the problematic situation. Out-of-order (OOO) execution is a ramification of the stall approach since it executes the instruction in an order governed by the availability of the input data rather than by their original order in the program. This paper presents a new algorithm called Left-Right (LR) for reducing stalls in pipelined processors. This algorithm is built by combining the traditional in-order and the out-of-order (OOO) instruction execution, resulting in the best of both approaches. As instruction input, we take the Tomasulo’s algorithm for scheduling out-of-order and the in-order instruction execution and we compare the proposed algorithm’s efficiency against both in terms of power-performance gain. Experimental simulations are conducted using Sim-Panalyzer, an instruction level simulator, showing that our proposed algorithm optimizes the power-performance with an effective increase of 30% in terms of energy consumption benefits compared to the Tomasulo’s algorithm and 3% compared to the in-order algorithm.

Highlights

Instruction pipeline is extensively used in modern processors in order to achieve instruction level parallelism in pipelined processor architectures [1]
Our algorithm introduces a hybrid order of instruction execution in order to reduce the power dissipationl
We have presented a stall reduction algorithm for optimizing the power-performance in pipelined processors

Summary

Introduction

Instruction pipeline is extensively used in modern processors in order to achieve instruction level parallelism in pipelined processor architectures [1]. Various approaches can be to increase the pipeline stages, and various strategies can be used to reduce the stalls caused by the pipeline hazards To solve this hazard, one can use a large and faster buffer to fetch the instructions and perform an out of order execution. In order to overcome this issue, we have uses an out-of-order (OOO) method which is the traditional way to increase the efficiency of pipelined processors by maximizing the instruction issued by every cycle [24] This technique is very costly in terms of its implementation. If a buffer in presence can hold a certain number of sequential instructions, our algorithm will generate a sequence in which the instructions should be executed to reduce the number of stalls while maximizing the throughput of a processor. Algorithm 2 Actual Instruction execution of proposed algorithm LR(Left-Right) vs. Inorder, Tomasulo

1: Instructions

Findings

Conclusions