An Optimized Nature-Inspired Metaheuristic Algorithm for Application Mapping in 2D-NoC.

Naveed Khan Baloch,Waqar Amin,Fawad Hussain,Heejung Yu,Yousaf Bin Zikria,Saleha Sikandar

doi:10.3390/s21155102

Abstract

Mapping application task graphs on intellectual property (IP) cores into network-on-chip (NoC) is a non-deterministic polynomial-time hard problem. The evolution of network performance mainly depends on an effective and efficient mapping technique and the optimization of performance and cost metrics. These metrics mainly include power, reliability, area, thermal distribution and delay. A state-of-the-art mapping technique for NoC is introduced with the name of sailfish optimization algorithm (SFOA). The proposed algorithm minimizes the power dissipation of NoC via an empirical base applying a shared k-nearest neighbor clustering approach, and it gives quicker mapping over six considered standard benchmarks. The experimental results indicate that the proposed techniques outperform other existing nature-inspired metaheuristic approaches, especially in large application task graphs.

Highlights

The overall performance and scalability of the system-on-chip (SoC) are degraded because of the increasing number of intellectual property (IP) cores embedding on the SoC.For the improvement of overall performance and flexibility of the SoC, new promising solutions have been proposed, and they are called network-on-chip (NoC) [1]
This paper presents a state-of-art nature-inspired metaheuristic algorithm, i.e., sailfish optimization algorithm (SFOA), which mainly comprises two advantages
The second advantage is robust optimization by strengthening the search space intended for the diversity of the sardine population

Summary

Introduction

For the improvement of overall performance and flexibility of the SoC, new promising solutions have been proposed, and they are called network-on-chip (NoC) [1]. NoC is an on-chip, packet-based communication switching network which is created for interaction between IP cores of the SoC designs [2]. The authors of [3,4,5,6] did some architectural modifications in the existing NoC routers designs to propose a reliable on-chip network communication infrastructure. As per the multi-core system principle, the contribution of NoC in power consumption of the total system is around 40%, and this has a vital role in network performance [1,7]. The power, latency and area of NoC-based systems are conspicuously impacted by the selection of an on-chip interconnection architecture [7]

Methods

Results

Conclusion