An optimized linear skewing interleave scheme for on-chip multi-access memory systems

Abstract

An optimized linear skewing interleave scheme for on-chip multi-access memory systems is proposed in this paper. The proposed scheme can support simultaneous access of multiple subarray types of data elements in a 2-D data space with modulo addressing. 2pq (pq is the number of data elements in a subarray) memory modules are used without redundancy to save the on-chip memory. It uses linear skewing in the horizontal direction and uses nonlinear skewing in the vertical direction. Fast implementation method for the proposed scheme is also described. Results show that compared to previous linear skewing schemes, the proposed scheme can reduce 13.6%, on average, of the on-chip memory for cases of pq = 4 or 8 and reduce 35.5%, on average, of the external memory bandwidth for benchmark of motion estimation due to modulo addressing.