An optimized hybrid approach to provide fault detection and correction in SoCs

Abstract

An increasing number of safety-critical applications are based on Systems-on-Chip (SoCs), thus pushing a new wave of research aiming at the development of suitable techniques for ensuring their reliability. Several fault tolerance techniques have been proposed to ensure their fault detection capabilities, based either on software-based or hardware-based techniques. In this paper, we propose an optimized version of a recently proposed hybrid approach, which is able to provide fault detection and correction capabilities with respect to transient faults for processor-based SoCs. The proposed solution exploits some modifications of the source code at high level and an Infrastructure IP (I-IP). The main advantage of the proposed method lies in the fact that it does not require any modification of the microprocessor core. Experimental results show that the proposed method can guarantee fault coverage mainly at the same cost of the original method providing fault detection, only.