Abstract
The reliability of Systems-on-Chip (SoCs) is very important with respect to their use in different types of critical applications. Several fault tolerance techniques have been proposed to improve their fault detection and correction capabilities. These approaches can be classified in two basic categories: software-based and hardware-based techniques. In this paper, we propose a hybrid approach to provide fault detection and correction capabilities of transient faults for processor-based SoCs. This solution improves a previous one, aimed at fault detection only, and combines some modifications of the source code at high level with the introduction of an Infrastructure Intellectual Property (TIP). The main advantage of the proposed method lies in the fact that it does not require modifying the microprocessor core. Experimental results are provided to evaluate the effectiveness of the proposed method.
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