An optimized hardware architecture for intra prediction for HEVC

Abstract

In this paper, we propose an optimized hardware architecture for the implementation of intra prediction in High Efficiency Video Coding standard (HEVC) decoder developed by the Joint Collaborative Team on Video Coding (JCT-VC) which is the common group released by the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. HEVC is designed to achieve better coding efficiency and compression ratio relative to H.264/AVC (Advanced Video Coding), but also involves increasing in complexity. As in previous standards, the intra prediction in HEVC is the process of reconstructing blocs based on neighboring pixels located above and in the left of the current bloc. The complexity of intra prediction is especially manifested with the increasing of flexibility in coding unit structures and the number of prediction modes. In fact, the final version of working draft (HM) test model defines 35 modes for all prediction units PU instead of 9 modes for intra-4×4 and 4 modes for intra-16×16 in H.264/AVC. This paper presents a new optimized hardware architecture for the implementation of al directional modes of intra prediction 4×4 in HEVC standard. This architecture is designed with Modelism simulator and synthesized using TSMC 0.18um CMOS and Xilinx Virtex 6 FPGA technologies. It needs 15010 logic gates and runs at 218 MHZ when using 0.18um CMOS technology. In other hand, the number of slice is about 1654 LUTS and the frequency operation is 234 MHZ with Xilinx Virtex 6 FPGA .