High-performance multiplierless DCT architecture for HEVC

Abstract

There are numerous video compression format for storage or transmission of digital video content. High Efficiency Video Coding (HEVC) is a video compression standard, a successor to H.264/MPEG-4 Advanced Video Coding (AVC), that was jointly developed by the ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) as ISO/IEC 23008-2 MPEG-H Part 2 and ITU-T H.265. In this paper, we propose an efficient architecture for the computation of 4, 8, 16 and 32 point DCT used in HEVC standard. The architecture uses the Canonical Signed Digit (CSD) representation and Common Sub-expression Elimination (CSE) technique to perform the multiplication with shift-add operation. The proposed architecture requires less number of adders and shifters and gives almost double throughput as compared to the previous work. Number of Logic Elements (LEs) required for the implementation is reduce by almost 36% without compromising throughput. The hardware cost reduces due to the reduction in arithmetic operation.