Abstract
In this paper, an optimized direct digital frequency synthesizer (DDFS) utilizing even fourth order polynomial is introduced. The spurious free dynamic range (SFDR) upper bound of the design is evaluated and an optimized digital system is designed to implement the method. It is shown that SFDR of the implemented digital system is 72.2dBc, which is only 2.15dBc less than the theoretical SFDR upper bound. Finally, the proposed system is realized in a chip using a 0.13/spl mu/m standard cell library. The maximum clock frequency, the chip area and the chip power consumption are calculated equal to 210 MHz, 1048/spl mu/m/sup 2/ and 11.57 /spl mu/W/MHz, respectively.
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