A High-Speed Low-Power Low-Latency Pipelined ROM-Less DDFS

Abstract

The present-day research on direct digital frequency synthesizer (DDFS) lays emphasis on ROM-less architecture, which is endowed with high speed, low power and high spurious free dynamic range (SFDR) features. The DDFS has a wide application in signal processing and telecommunication area, which generates the sine or cosine waveforms within a broad frequency range. In this paper, one high-speed, low-power, and low-latency pipelined ROM-less DDFS architecture has been proposed, implemented and tested using Xilinx Virtex-II Pro University FPGA board. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with a maximum amplitude error of 1.5 ×10− 4. FPGA implementation of the proposed design has exhibited an SFDR of -94.3 dBc and a maximum operating frequency of 276 MHz while consuming only 22 K gates and 1.05 mW/MHz power. The high speed of operation and the low power make the proposed design suitable for use in communication transceiver for up and down conversion.