An optimized design of under-sampling 100MHz-10b time-interleaved pipelined ADC

Abstract

An under-sampling high speed pipelined ADC is proposed with optimized two-channel time-interleaved architecture. The two channels have a common SHA which is designed for under-sampling while the clock frequency in each channel is half of it in SHA. And in the two-channel time-interleaved pipelined part, the shared operational amplifier compensates for the large mismatch between the channels in each same stage. This design minimizes power consumption and chip area in time-interleaved ADC. Under SMIC 0.35um 1P6M process with 3.3V supply, the performance of SNR reaches nearly 65dB with the condition that the sampling rate is 100MHz and the input frequency is scanned from 1MHz to 110MHz. The current consumption of 100MSps is about 34mA.