Abstract
A pipelined ADC using shared amplifiers in two-channel time-interleaved design is proposed. The two channels have a unify sample and hold amplifier. In the time-interleaved pipelined part, the large mismatch between the channels is reduced by the shared amplifier in the same stage. And power consumption and chip area also been decreased. Under SMIC 0.35um 1P6M CMOS process with 3.3V supply, the SNR is higher than 60dB with the condition that the sampling rate is 200MHz and the input frequency is scanned from 1MHz to 80MHz. The typical current consumption is about 40mA.
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