Abstract
This paper presents a cost-effective VLSI architecture for a two-dimensional (2-D) inverse discrete cosine transform (IDCT) core based on a modified on-line CORDIC algorithm. In order to have a low hardware complexity and to provide a good performance, the proposed design is based on the row-column decomposition approach and distributed arithmetic (DA). By reformulating the 1-D IDCT functions using the CORDIC approach, the proposed design requires about 60% less ROM than the conventional DA-based IDCT without using CORDIC. In our architecture the on-line algorithm is used to further reduce the area and to enhance the computation speed. The core operates on blocks of 8/spl times/8 pixels, with 12-bit and 8-bit precision for inputs and outputs, respectively. The proposed design has been synthesized by using 0.35-/spl mu/m CMOS technology. The simulation results show that the core for IDCT can run at 150 MHz with 60 Mpixel/s throughput, while meeting the requirement of the H.26x standard.
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