An on-chip self-test architecture with test patterns recorded in scan chains

Abstract

This work proposes a novel test architecture that combines the advantages of both scan-based and built-in self-test (BIST) designs. The main idea is to record (store) all required compressed test data in a novel scan chain structure such that the stored data can be extracted, reconstructed and decompressed into required deterministic patterns using an on-chip test controller with a test pattern decompressor. The recording of test data is achieved by modifying the connections between scan cells. Techniques to extract test data from the modified scan cells and to deliver decompressed test patterns to the modified scan cells are presented. The on-chip test controller can automatically generate all required control signals for the whole test procedure. This significantly reduces the requirements on external ATE. Experimental results on OpenSPARC T2, a publicly accessible 8-core processor containing 5.7M gates, show that all required test data for 100% testable stuck-at fault coverage can be stored in the scan chains of the processor with less than 3% total area overhead for the whole test architecture.