An occurrence mechanism and method for improving the output waveform distortion of CMOS logic ICs

Abstract

Waveform distortion at a signal edge generally falls into two categories: hysteresis type and non-hysteresis type. Non-hysteresis type distortion has a flat portion in the signal transition, but it will not give any serious problem except for timing oriented circuits. Hysteresis type distortion which makes a round trip between two threshold levels will affect logic judgment. Incorrect information will be transmitted if the signal is seriously distorted. It is important to understand the relationship between spectrum modification and waveform distortion. In this paper, an occurrence mechanism for the output waveform distortion of CMOS logic ICs is analyzed and an improved method for dealing with these distortions is proposed. Waveform distortion occurs when series resonance circuits are composed on the load side of the driving device. The relationship between the rise time per period [%] and the limit frequency at which waveform distortion begins to appear will be made clear. There are two methods to improve waveform distortion. One is to change the spectrum distribution of a rectangular wave by modifying the rise time. The other is to change the resonance frequency by modifying such parasitic elements as inductance (pattern length) and capacitance (number of ICs). © 1998 Scripta Technica. Electr Eng Jpn, 123(3): 11–18, 1998