A study of the occurrence mechanism for undershoot of logic signal

Abstract

AbstractWaveform distortion of logic signal caused by accelerated clock speed and increased implementation density causes nonlinear output and has been responsible for behavioral problems in electronic systems, including the overshoot type, hysteresis type, and undershoot type of transient waveform distortion. Deep undershoot could cause latchup of CMOS logic ICs, data destruction in DRAM, and pulse splitting in TTL ICs. Undershoot of logic signals is discussed in terms of both transient phenomena (time domain) and filter theory (frequency domain). Variation of the resistance R caused by output circuit impedance variation creates time domain variations in such quantities as the damping constant α and damping coefficient ζ, while variation of resistance R creates Q variation in the frequency domain.This paper describes a mechanism by which undershoot occurs when parasitic series resonance circuits are formed on the load side of the driving device and the damping coefficient ζ varies time‐sequentially in totem‐pole or complementary circuits. PSpice simulation suggests that undershoot can be reduced by controlling the phase of the punchthrough current. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 142(3): 41–48, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.10141