An O(1) time complexity sorting network for small number of inputs with hardware implementation

Abstract

The sorting algorithms have found applications in various research fields including image and video processing. High speed sorting is important in real-time applications, such as real-time image processing. Two properties are criterion for sorting networks: the number of steps (speed) and the number of comparators (efficiency). In this paper, we have proposed a method to decrease the number of steps. We introduce a new method for sorting an unordered sequence, which is based on the graph theory concept,and contrary to the conventional sorting networks, it consists of graph edge calculators rather than compare-and-swaps. An outstanding feature of the proposed method is that for small number of inputs, its number of steps is independent of the number of inputs that denotes it orders N inputs in O(1) steps. Moreover, the proposed method surpasses the previous ones in term of speed; it just needs two steps to sort a sequence. In the first step, all the inputs are compared with each other, and in the second step, the results of comparisons direct the inputs to the right outputs. To justify the functionality, the proposed method is simulated with the Modelsim-Altera and implemented on a Cyclone IV FPGA platform. Simulation results indicate that in comparison with the Bather's Bitonic mergesort, which is known to be the fastest algorithm, the proposed method while requires 80% more LEs, consumes 52% less memory and achieves 73% more throughput. Furthermore, the Bitonic mergesort can only accept a power of 2 number of inputs, while the proposed method does not hold such a limitation.